(1) Field of the Invention
The present invention relates to semiconductor devices and methods for fabricating the same, and more particularly relates to MIS transistors and methods for forming the same.
(2) Description of Related Art
In recent years, with an increase in the degree of integration, functionality and speed of semiconductor integrated circuit devices, there have been demands for miniaturization in the size of transistors and increase in the driving force thereof. Meanwhile, there have been demands for low-power-consumption semiconductor permitting a reduction in energy consumption and long-time use of mobile equipment. It has become impossible to enhance the driving force of transistors only by reducing the gate length of the transistors. In a case where a gate insulating film of a transistor is reduced in thickness to enhance the driving force thereof, this increases the gate leakage current. To cope with this, a technique has been suggested in which a stress-applying film is formed to allow application of stress to the channel of a transistor, resulting in the enhanced driving force of the transistor.
FIGS. 14A through 14D are cross-sectional views illustrating process steps in a known fabrication method for a semiconductor device (see, for example; S. Ito et al., IEDM 2000, page 247). In the known fabrication method for a semiconductor device, first, in the process step illustrated in FIG. 14A, an isolation region 202 is formed in the upper portion of a semiconductor substrate 201, and then a gate insulating film 203 is formed on an active region of the semiconductor substrate 201. Thereafter, a gate electrode 204 is formed on the gate insulating film 203, and source/drain (SD) extension diffusion regions 205 are formed in the upper portion of the semiconductor substrate 201 using the gate electrode 204 as a mask. Thereafter, a silicon oxide film 206a and a silicon nitride film 207a are formed to cover the semiconductor substrate 201 and the gate electrode 204.
Next, in the process step illustrated in FIG. 14B, the silicon oxide film 206a and the silicon nitride film 207a are subjected to anisotropic etching, thereby forming sidewalls 206 and 207 on both sides of the gate electrode 204. Thereafter, source/drain regions 208 are formed by implanting ions from above the gate electrode 204 and the sidewalls 206 and 207 into the semiconductor substrate 201.
Next, in the process step illustrated in FIG. 14C, a tensile SiN film 209 is deposited on the entire substrate area.
Subsequently, in the process step illustrated in FIG. 14D, an interlayer dielectric 210 is deposited and planarized. Thereafter, contact holes 211 are formed in the interlayer dielectric 210 by lithography and then filled with tungsten, thereby forming contacts 212.
However, in the known semiconductor device, stress caused by the tensile SiN film 209 has insufficiently traveled to channel regions of the semiconductor device, and as a result the driving force of the semiconductor device has not been sufficiently enhanced.